parallel adder

optoelectronic parallel adder/ subtractor

光电并行加/减运算器

in the first stage, the amplitude sequence of modulating signal is generated by addressing waveform memory and added by the frequency value of carrier wave in the adder. the parallel output of the adder is served as the frequency control word of the second phase accumulator.

在第一级寻址结构中产生的调制信号幅度序列和载波频率值在加法器中相加，并将相加的结果作为第二级相位累加器的频率控制字；

the adder is the core of the alu, and its performance greatly influence to the performance of the entire alu, so we laid a strong emphasis on the design of sub-word parallel adder.

由于加法器是ALU单元的核心功能部件，它的性能决定着整个ALU单元的性能，所以本文主要对子字并行加法器进行了设计。

the logic operations of pd-led are studied. and experiment of optical parallel carry lookahead adder for many bits is carried out, with satisfactory results.

研究了PD-LED的光电混合逻辑操作，利用PD&LED逻辑器件，从实验上验证了先行进位光学并行多位全加器，获得了满意的结果。

research and implementation of parallel prefix adder

并行前缀加法器的研究与实现

A fast 64 bit binary parallel adder for high performance microprocessors and DSP processors is presented.

介绍了一个用于高性能的微处理器和DSP处理器的快速64位二进制并行加法器.

research on a parallel adder with 4 binary addends and its interface

4个加数的并行加法器及扩展接口的研究

this paper introduces the design method of parallel adder. on the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement, through logic synthesis and layout.

首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。